The present invention relates generally to testing of integrated circuits. More particularly, the present invention relates to a method and apparatus for measuring subthreshold current in a memory array.
There is a need to test the operation of memory cells in a memory device. Operation is related to the performance (reading, erasing, writing) of memory cells and to the consistent operation of memory cells. By testing operation of a cell or a group of cells, the design of a memory device can be characterized and improved.
One example occurs in a flash memory configured as a memory cell array of 512 word lines by 1024 or more columns or bit lines. A single row or word line is selected by address decoding circuitry. When selected, the word line is at a voltage near V.sub.cc, the positive supply voltage of the integrated circuit. Deselected word lines remain near ground potential.
In this condition, the unselected cells may draw substantial current. Subthreshold or leakage current is undesirable and occurs for example, because of an over erase condition of the memory cell. Further, subthreshold current occurs because of variation in threshold voltage (V.sub.t) of the transistors in the memory cells. While the subthreshold current in an individual memory cell is small, on the order of 100 nA, in a large memory, the subthreshold current in an entire column of memory cells may total 1-3 .mu.A. This is substantial compared to the read current in a memory cell required to activate a sense amplifier to read the state of the selected cell. Characterization of the subthreshold current allows determination of the portion of current in the sense amplifier due to subthreshold current.
Previously, subthreshold current has been characterized using a test structure on an integrated circuit. The test structure has, for example, 512 memory cells arranged in a column with terminals for applying and reading voltages and other signals. While this is effective at obtaining data, this setup has some limitations. An actual integrated circuit does not always behave the same way as a test structure. For example, a bit line in a sector of the memory cell array with a slow bit behaves differently from a normal bit line in another sector. Moreover, the prior art setup took as much as a week for full collection of data. The prior art testing technique only permits indirect measurement of data rather than measurement of data in an actual memory product.
Accordingly, there is a need for an improved method and apparatus for testing memory devices.